Meet Subhasish Mitra and Tathagata Srimani: Indian-origin professors build America’s first monolithic 3D AI chip

Indian-origin professors Subhasish Mitra of Stanford University and Tathagata Srimani of Carnegie Mellon University are at the centre of a breakthrough that could reshape how artificial intelligence hardware is built in the United States.

Along with a multi-institutional team spanning Stanford, Carnegie Mellon, the University of Pennsylvania and MIT, they have developed America’s first monolithic 3D AI chip fabricated in a US commercial foundry. Announced recently and presented at a leading semiconductor conference, the work demonstrates clear performance gains over traditional designs and points to a new direction for faster, more energy-efficient AI systems.

In simple terms, they have found a new way to build computer chips that allows AI systems to run much faster while using far less energy.

Who are Subhasish Mitra and Tathagata Srimani

Subhasish Mitra is a senior figure in global chip research and a long-time leader in advanced electronics. He is the William E. Ayer Professor of Electrical Engineering and Computer Science at Stanford University, where his work focuses on reliable nanoelectronics, hardware security and three-dimensional chip integration.

Mitra has spent decades tackling some of the hardest problems in chip design, including how to make increasingly complex hardware both faster and more dependable.

Describing the new monolithic 3D chip, he said: “This opens a new era in chip production and innovation,” reflecting years of research aimed at rethinking how chips are built from the ground up.

Tathagata Srimani, now an assistant professor of Electrical and Computer Engineering at Carnegie Mellon University, was previously a postdoctoral researcher under Mitra at Stanford.

He holds a BTech degree from the Indian Institute of Technology Kharagpur and has built a research career around energy-efficient computing and hardware architectures for AI. Srimani played a central role in advancing the idea of stacking memory and compute vertically, helping turn a theoretical concept into a working, manufacturable chip.

Together, Mitra and Srimani represent a rare combination of deep academic expertise and practical engineering insight.

Their collaboration shows how long-term university research, when paired with real-world manufacturing partners, can lead to breakthroughs that shape the future of technology rather than remaining confined to the laboratory.

Breaking AI chips’ biggest bottleneck: The memory wall

Modern AI systems struggle not because they lack computing power, but because of how information moves inside a chip. In today’s flat, two-dimensional chips, data has to travel back and forth between memory, where information is stored, and processors, where calculations happen.

This constant movement is slow and energy-intensive, creating what engineers call the “memory wall”. As AI models grow larger, this bottleneck becomes even more severe.To address this, the team adopted a vertically stacked design, which researchers involved in the project have compared to a high-rise structure. Instead of spreading memory and computing units across a flat surface, they are placed on top of each other.

Ultra-dense vertical connections act like elevators, allowing data to move directly between layers. This sharply reduces the distance data must travel, enabling faster operation and lower power consumption.Many chips today are marketed as “3D”, but most rely on packaging techniques that stack completed chips together. This work is fundamentally different. The layers are built together as a single unit at the microscopic level, creating a truly monolithic structure.

Because everything is tightly integrated, the chip behaves like one system rather than multiple components joined after fabrication, which is what enables the substantial performance gains.Tests on the prototype chip showed around four times higher throughput than comparable flat chips of similar size and latency. While these gains were demonstrated on the working hardware, simulations suggest that larger, scaled versions could deliver up to 100–1,000× improvements in energy–delay product for demanding AI workloads such as large language models, indicating far greater efficiency rather than raw speed alone.Another major milestone is where the chip was made. The entire fabrication process took place at SkyWater Technology, the largest exclusively US-based pure-play semiconductor foundry. Earlier versions of monolithic 3D chips existed only in research labs. Demonstrating this technology in a commercial US foundry shows it can be realistically scaled, supporting broader efforts to strengthen domestic semiconductor manufacturing.

Why this matters for the future of AI

As AI systems become more powerful, traditional chip designs are approaching their limits. This new approach offers a practical path forward by reducing data movement, improving efficiency and lowering energy costs. It also reduces reliance on overseas chip manufacturing at a time when advanced semiconductors are increasingly tied to economic competitiveness and national security.The team is now working on scaling the design to include more layers and support more complex AI workloads. If future chips match the early results suggested by simulations, monolithic 3D architectures could become a foundation for next-generation AI hardware. For now, the work stands as a clear example of how rethinking the fundamentals of chip design can unlock major advances in artificial intelligence.